Method for manufacturing a vertical-gate MOS transistor with...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S589000, C257SE21419

Reexamination Certificate

active

07572703

ABSTRACT:
A method manufactures a vertical-gate MOS transistor integrated in a semiconductor chip having a main surface. The method includes: forming a trench gate extending into the chip from the main surface to a gate depth, by forming a control gate and an insulation layer for insulating the control gate from the chip. Forming the trench gate includes: forming a trench extending into the chip from the main surface to a protection depth less than the gate depth, the trench having a lateral wall and a bottom wall with an edge portion of the lateral wall extending from the main surface being inclined outwardly with respect to the remaining portion of the lateral wall; forming a first auxiliary insulation layer in the trench; removing a bottom wall of the first auxiliary insulation layer; extending the trench to the gate depth; and forming a second auxiliary insulation layer in the trench.

REFERENCES:
patent: 4455740 (1984-06-01), Iwai
patent: 4914058 (1990-04-01), Blanchard
patent: 5124764 (1992-06-01), Mori
patent: 5371024 (1994-12-01), Hieda et al.
patent: 6586800 (2003-07-01), Brown
patent: 2002/0153558 (2002-10-01), Takemori et al.
patent: 2005/0014337 (2005-01-01), Hadizad

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