Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-07-24
2009-08-25
Luu, Chuong A. (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S295000, C257S310000, C257S410000
Reexamination Certificate
active
07579227
ABSTRACT:
A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.
REFERENCES:
patent: 6642071 (2003-11-01), Cheng
patent: 6929992 (2005-08-01), Djomehri et al.
patent: 6992358 (2006-01-01), Hieda et al.
patent: 2003/0022422 (2003-01-01), Torii et al.
patent: 2004/0004234 (2004-01-01), Yagishita et al.
patent: 2004/0129997 (2004-07-01), Morifuji
patent: 2005/0121733 (2005-06-01), Chen et al.
patent: 2005/0127436 (2005-06-01), Henson et al.
patent: 2006/0121740 (2006-06-01), Sakai et al.
patent: 1610129 (2005-04-01), None
patent: 2004-356576 (2004-12-01), None
patent: 2005-064190 (2005-03-01), None
Watanabe, Ken, Partial English Translation of “HfSiON-CMOS technology for achieving high performance and high reliability,” Semi Forum Japan, 2005, IT System & ULSI Technology.
Hori, Takashi, “¼-μm LATID (LArge-Tilt-angleImplantedDrain) Technology For 3.3-V Operation”, CH2637-7/89/0000-0777 1989 IEEE, IEDM 89-777-780-IEDM 89.
Sayama, et al., H.,, “80nm CMOSFET Technology Using Double Offset-Implanted Source/Drain Extension and Low Temperature SiN Process”, IEDM 2000, IEDM 00-239-242-IEDM 00.
Chinese Office Action, with English Translation, issued in Chinese Patent Application No. CN 200610093872.2, dated Mar. 20, 2009.
U.S. Office Action issued in U.S. Appl. No. 11/543,865, filed Nov. 12, 2008.
Aida Kazuhiko
Hirase Junji
Kotani Naoki
Okazaki Gen
Sebe Akio
Luu Chuong A.
McDermott Will & Emery LLP
Panasonic Corporation
LandOfFree
Semiconductor device and method for fabricating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method for fabricating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method for fabricating the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4117151