Method of forming transistor structure having stressed...

Details Method of forming transistor structure having stressed... Method of forming transistor structure having stressed...

2007-07-16

2009-08-04

Pham, Thanhha (Department: 2894)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S275000, C257SE21632

Reexamination Certificate

active

07569447

ABSTRACT:
A method of fabrication is provided in which a field effect transistor (FET) is formed having a channel region and source and drain regions adjacent to the channel region. A first stressed region underlies the channel region, in which the first type of stress is either compressive type or tensile type. Second stressed regions having a second type of stress underlie the source and drain regions, in which the second type of stress is an opposite one of the compressive type or tensile type stress of the first stressed region.

REFERENCES:
patent: 2006/0003597 (2006-01-01), Golonzka et al.

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