Method of manufacturing semiconductor device having cell...

Details Method of manufacturing semiconductor device having cell... Method of manufacturing semiconductor device having cell...

2008-10-23

2009-11-24

Huynh, Andy (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S270000, C438S271000, C438S589000, C257S330000, C257SE21428, C257SE21429

Reexamination Certificate

active

07622350

ABSTRACT:
A method of manufacturing a semiconductor device is provided. Device separation portions defining first, second and third regions are formed in a substrate. A recess is formed at the first region. An N-type well is formed at the third region. An N-type polysilicon layer is formed at the first and second regions. A P-type polysilicon layer is formed at the third region. At least one of metal silicide film and a metal film is formed on the N-type polysilicon layer and the P-type polysilicon layer. Etching is performed to form a gate electrode including the N-type polysilicon layer at the first and second regions and a gate electrode including the P-type polysilicon layer at the third region. A cell transistor having a recess channel structure is formed at the first region, an nMOSFET structure is formed at the second region, and a pMOSFET structure is formed at the third region.

REFERENCES:
patent: 6218235 (2001-04-01), Hachisuka et al.
patent: 6844578 (2005-01-01), Harada et al.
patent: 7023054 (2006-04-01), Ohsawa
patent: 7109536 (2006-09-01), Nakabayashi
patent: 06-275788 (1994-09-01), None
patent: 11-307729 (1999-11-01), None
patent: 2002-261256 (2002-09-01), None
patent: 2002-359294 (2002-12-01), None
Japanese Office Action, with partial English translation, issued in Japanese Patent Application No. 2005-151641, mailed Aug. 19, 2009.

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