Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-07-23
1999-06-15
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438307, 438656, 438763, H01L 21336
Patent
active
059131217
ABSTRACT:
On a surface of a silicon substrate having conductivity type of p-type, a field oxide layer and a gate oxide layer to be an isolation region are formed. A gate electrode is formed via the gate oxide layer. A surface silicon oxide layer is formed on a surface of the gate electrode. An etch stop layer is formed at a region outside of the surface silicon oxide layer, which etch stop layer is formed of a material different from a material of the gate oxide layer. Also, on the upper surface of the etch stop layer, an interlayer insulation layer is formed. Then, on the surface of the silicon substrate in the vicinity of the end of the gate electrode, an n.sup.- -diffusion layer is formed. In a region outside of the n.sup.- -diffusion layer, an n.sup.+ -diffusion layer is formed. On the other hand, between the upper surface of the n.sup.- -diffusion layer and the n.sup.+ -diffusion layer and the lower end of the etch stop layer, a bottom silicon oxide layer having greater layer thickness than the gate oxide layer is formed. A wiring and the n.sup.+ -diffusion layer are connected each other via the contact hole formed in the interlayer insulation layer.
REFERENCES:
patent: 5032535 (1991-07-01), Kamijo et al.
patent: 5650344 (1997-07-01), Ito et al.
patent: 5668028 (1997-09-01), Bryant
patent: 5776822 (1998-07-01), Fujii et al.
Japanese Office Action dated Sep. 11, 1998 with English language translation of Japanese Examiner's comments.
Mizuno, T., et al., "Hot-carrier injection suppression due to the nitride-oxide LDD spacer structure," IEEE Transactions on Electron Devices, vol. 38, No. 3, pp. 584-591, Mar. 1991.
Chaudhari Chandra
NEC Corporation
LandOfFree
Method of making a self-aligning type contact hole for a semicon does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making a self-aligning type contact hole for a semicon, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a self-aligning type contact hole for a semicon will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-409896