Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-06-26
1999-06-15
Nguyen, Tuan H.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438396, 438398, 438253, H01L 218242
Patent
active
059131195
ABSTRACT:
A process creating a crown shaped storage node electrode, for high density, DRAM designs, has been developed. The process features the formation of an hemispherical grain, (HSG), silicon layer, only on the outside walls of the amorphous silicon vertical shapes, of the crown shaped storage node electrode. The HSG silicon layer is formed from HSG silicon seeds, and from undoped, or lightly doped amorphous silicon layers, or a combination of both. The amorphous silicon vertical shapes are comprised of an undoped, or lightly doped amorphous silicon layer, placed as the outside layer, while a heavily doped amorphous silicon layer is used for the inside layer. This configuration therefore only allows the formation of the HSG silicon layer on the outside walls of the amorphous silicon vertical shape, and therefore results in a crown shaped storage node electrode, with a minimum space between vertical shapes maintained, and not compromised by encroaching HSG silicon layers, that would have been formed on the inside surfaces of the vertical shapes, if a heavily doped amorphous silicon layer were not present.
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Chang Jung-Ho
Chen Hsi-Chuan
Lin Dahcheng
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