Method of manufacturing trench DRAM cells with self-aligned fiel

Details Method of manufacturing trench DRAM cells with self-aligned fiel Method of manufacturing trench DRAM cells with self-aligned fiel

1997-12-12

1999-06-15

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438246, H01L 218242

Patent

active

059131187

ABSTRACT:
A silicon oxide, a silicon nitride layer are patterned to define trenches region. Then, a recess portion is formed in the substrate. Subsequently, a second silicon oxide, a second silicon nitride layer are formed on the recess portion. Then, a glass layer is formed on the second silicon nitride layer and refilled into the recess portion. An etching step is performed to etch the glass layer, the second silicon nitride layer and the second silicon oxide layer to the surface of the substrate. Trenches are then created in the substrate. Then, ion implantation processes are performed to dope ions into the trenches. A dielectric layer is then deposited along the surface of the trenches and on the surface of the second silicon oxide layer, the second silicon nitride layer. A polysilicon layer is deposited on the dielectric layer and refilled into the trenches. Then, an etching back is used to etch the polysilicon layer to form a field plate. Successively, a thermal process is carried out to form an oxide layer on the field plate. Next, side-wall spacers are formed on the side walls of the field plate, and the oxide layer.

REFERENCES:
patent: 5111259 (1992-05-01), Teng et al.
patent: 5432113 (1995-07-01), Tani

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