Non-planar non-volatile memory cell with an erase gate, an...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S267000, C257SE21422, C257SE21680, C257SE21685, C257SE21689, C257SE21693

Reexamination Certificate

active

07547603

ABSTRACT:
A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.

REFERENCES:
patent: 5029130 (1991-07-01), Yeh
patent: 5780341 (1998-07-01), Ogura
patent: 5856943 (1999-01-01), Jeng
patent: 6091104 (2000-07-01), Chen
patent: 6329685 (2001-12-01), Lee
patent: 6972260 (2005-12-01), Huang et al.

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