Fin structure and method of manufacturing fin transistor...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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C438S311000, C438S753000, C257SE21170, C257SE21320, C257SE21245, C257SE21304, C257SE21229, C257SE21347, C257SE21411

Reexamination Certificate

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07575962

ABSTRACT:
Provided are a fin structure and a method of manufacturing a fin transistor adopting the fin structure. A plurality of mesa structures including sidewalls are formed on the substrate. A semiconductor layer is formed on the mesa structures. A capping layer is formed on the semiconductor layer. Thus, the semiconductor layer is protected by the capping layer and includes a portion which is to be formed as a fin structure. A portion of an upper portion of the capping layer is removed by planarizing, and thus a portion of the semiconductor layer on upper surfaces of the mesa structures is removed. As a result, fin structures are formed on sides of the mesa structures to be isolated from one another. Therefore, a fin structure having a very narrow width can be formed, and a thickness and a location of the fin structure can be easily controlled.

REFERENCES:
patent: 6689650 (2004-02-01), Gambino et al.
patent: 6815738 (2004-11-01), Rim
patent: 6936516 (2005-08-01), Goo et al.
patent: 6943087 (2005-09-01), Xiang et al.
patent: 6949421 (2005-09-01), Padmanabhan et al.
patent: 7078299 (2006-07-01), Maszara et al.
patent: 2005/0048727 (2005-03-01), Maszara et al.

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