Modifying a test pattern to control power supply noise

Details Modifying a test pattern to control power supply noise Modifying a test pattern to control power supply noise

2006-09-13

2009-10-27

Jacques, Jacques H. Louis (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000, C714S728000, C714S729000, C714S738000, C714S739000

Reexamination Certificate

active

07610531

ABSTRACT:
Mechanisms for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a circuit voltage, e.g., an on-chip voltage, which approximates a nominal circuit voltage, such as produced by the application of other portions of the sequence of states in the same or different test sequences. For example, hold state cycles or shift-scan state cycles may be inserted or removed prior to test state cycles in the test pattern waveform. The insertion/removal shifts the occurrence of the test state cycles within the test pattern waveform so as to adjust the voltage response of the test state cycles so that they more closely approximate a nominal voltage response. In this way, false failures due to noise in the voltage supply may be eliminated.

REFERENCES:
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Nourani et al., Pattern Generation and Estimation for Power Supply Noise Analysis, 2005, IEEE, pp. 1-6.
Baker et al., Interconnect Test Pattern Generation Algorithm For Meeting Device and Global SSO Limits With Safe Initial Vectors, 2004, IEEE, paper .2, pp. 163-172.
Miczo, Alexander, Digital Logic Testing and Simulation (Second Edition), Aug. 29, 2003, 2nd, pp. 451-512.

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