Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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Details

C365S189011, C365S189040, C365S189160

Reexamination Certificate

active

07545683

ABSTRACT:
A semiconductor memory device arranged for minimizing the duration of time required for conducting a batch verify action and thus speeding up a buffer write action is provided. The device which conducts a write action to memory cells in an address area, a batch verify action for collectively conducting verify action for a plurality of addresses, and repeats the batch verify action and the write action, comprises a detecting means for detecting whether or not each address contains an unwritten memory cell, and conducts a verify action at least at a part of the batch verify action excluding at least a part of addresses judged not to contain unwritten memory cells by the verify action at one or more cycles before.

REFERENCES:
patent: 5886927 (1999-03-01), Takeuchi
patent: 6018478 (2000-01-01), Higuchi
patent: 6259630 (2001-07-01), Kawamura
patent: 6944093 (2005-09-01), Sumitani
patent: 2004/0193774 (2004-09-01), Iwata et al.
patent: 2004-039112 (2004-02-01), None
patent: 2001-0014760 (2001-02-01), None

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