Structure of wafer level package with area bump

Details Structure of wafer level package with area bump Structure of wafer level package with area bump

2007-11-05

2009-08-18

Clark, S. V (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S786000, C257S780000

Reexamination Certificate

active

07576436

ABSTRACT:
A package structure with an area bump has at least a chip (also known as a die), a redistribution layer, a plurality of first bumps (normal bumps) and at least a second bump (area bump). The redistribution layer may reroute and integrate the bonding pads of the chip and incorporate the passive components therein.

REFERENCES:
patent: 6433427 (2002-08-01), Wu et al.
patent: 6586844 (2003-07-01), Chang
patent: 6838776 (2005-01-01), Leal et al.
patent: 6845554 (2005-01-01), Frankowsky et al.
patent: 2005/0098802 (2005-05-01), Kim et al.

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