Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-10-26
2009-02-17
Dang, Phuc T (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S151000, C438S585000, C257S288000, C257S347000
Reexamination Certificate
active
07491594
ABSTRACT:
A method of automatically generating planar double gate transistor shapes can include taking an integrated circuit layout design that includes single gate transistors, locating the gate shapes and active shapes for the transistors, generating top gate shapes, planar double gate active shapes, bottom gate shapes, active cavity shapes, source/drain cavity shapes, and top gate contact shapes, bottom gate contact shapes, thru-gate contact shapes, and source/drain contact shapes for the planar double gate transistors. The method can generate gate contact shapes that have top and bottom gates to be electrically connected within the same planar double gate transistor or separate gate contact shapes where the top and bottom gates are not electrically connected to each other. In one embodiment, a data processing system can include a program that has code in the form of instructions to carry out the method.
REFERENCES:
patent: 5097422 (1992-03-01), Corbin, II et al.
patent: 6099582 (2000-08-01), Haruki
patent: 6339002 (2002-01-01), Chan et al.
patent: 6662350 (2003-12-01), Fried et al.
patent: 6940096 (2005-09-01), Ravi
patent: 7013447 (2006-03-01), Mathew et al.
patent: 7074656 (2006-07-01), Yeo et al.
patent: 7315994 (2008-01-01), Aller et al.
patent: 2003/0145299 (2003-07-01), Fried et al.
patent: 2004/0161898 (2004-08-01), Fried et al.
patent: 2005/0285161 (2005-12-01), Kang et al.
patent: 2006/0017119 (2006-01-01), Jin et al.
patent: 2006/0064191 (2006-03-01), Naya et al.
patent: 2007/0083847 (2007-04-01), Mansfield et al.
Nowak, Edward, et al., “Turning Silicon on its Edge: Overcoming Silicon Scaling Barriers with Double-Gate and FinFET Technology,” IEEE Circuits & Devices Magazine, Jan./Feb. 2004, pp. 20-31.
Soloman, P.M., et al., “Two Gates are Better than One: A Planar Self-Aligned Double-Gate MOSFET Technology to Achieve the Best On/Off Switching Ratios as Gate Lengths Shrink,” IEEE Circuits & Devices Magazine, Jan. 2003, pp. 48-62.
U.S. Appl. No. 11/098,874, filed Apr. 5, 2005.
U.S. Appl. No. 10/971,657, filed Oct. 22, 2004.
U.S. Appl. No. 11/258,777, Office Action mailed Sep. 24, 2008.
Dang Phuc T
Freescale Semiconductor Inc.
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