Non-volatile memory device with high gate coupling ratio and man

Details Non-volatile memory device with high gate coupling ratio and man Non-volatile memory device with high gate coupling ratio and man

1997-04-11

1999-05-25

Booth, Richard A

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438593, H01K 218247

Patent

active

059077751

ABSTRACT:
A dielectric layer over a substrate is covered with a gate conductor mask and an organic polymer lining layer formed on the device narrows the mask opening to create a gate conductor molding trench by MERIE etching through the opening and dielectric down to the substrate. Then a gate oxide layer is formed. A conformal floating gate conductor is deposited over the device and down into the trench, narrowing the trench. A thin interelectrode dielectric layer covers the floating gate and further narrows the trench. A control gate layer covers the device and fills the trench. The floating gate, the interelectrode dielectric, and the control gate conductor are planarized down to the dielectric, which is stripped away. Then self-aligned source/drain regions are formed in the substrate. Semiconductor memory gate conductor stacks have increased surface area for improving the coupling ratio.

REFERENCES:
patent: 5459091 (1995-10-01), Hwang
patent: 5496753 (1996-03-01), Sakurai et al.
patent: 5556799 (1996-09-01), Hong
patent: 5567635 (1996-10-01), Acovic et al.
patent: 5583066 (1996-12-01), Jung
patent: 5614430 (1997-03-01), Liang et al.
patent: 5670401 (1997-09-01), Tseng
patent: 5707897 (1998-01-01), Lee et al.

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