System and method for advanced logic built-in self test with...

Details System and method for advanced logic built-in self test with... System and method for advanced logic built-in self test with...

2006-08-11

2009-06-09

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000, C714S733000, C714S728000

Reexamination Certificate

active

07546504

ABSTRACT:
A system and method for advanced logic built-in self test with selection of scan channels is present. An LBIST controller loads scan patterns into a device's scan channels through sequential or interleaved loading techniques in order to minimize instantaneous power requirements. During interleave loading, the LBIST controller loads a scan bit into a first scan chain, then into a second scan chain, etc. until one bit is loaded into each scan chain. The LBIST controller then returns to load another scan bit into the first scan channel, then the second scan channel, etc. During sequential loading, the LBIST controller loads an entire scan pattern into a first scan chain (one bit per clock cycle). Once the first scan pattern is loaded, the LBIST controller proceeds to load subsequent scan patterns into corresponding scan chains on a one bit per scan channel per clock cycle basis.

REFERENCES:
patent: 7155648 (2006-12-01), Jas et al.
patent: 2002/0194565 (2002-12-01), Arabi
patent: 2007/0168809 (2007-07-01), Kiryu et al.

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