Methods for fabricating an integrated circuit

Details Methods for fabricating an integrated circuit Methods for fabricating an integrated circuit

2006-12-28

2009-11-24

Sarkar, Asok K (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21646, C257SE21678, C438S256000, C438S399000, C438S678000

Reexamination Certificate

active

07622348

ABSTRACT:
Methods are provided for reducing the aspect ratio of contacts to bit lines in fabricating an IC including logic and memory. The method includes the steps of forming a first group of device regions to be contacted by a first level of metal and a second group of memory bit lines to be contacted by a second level of metal, the first level separated from the second level by at least one layer of dielectric material. Conductive material is plated by electroless plating on the device regions and bit lines and first and second conductive plugs are formed overlying the conductive material. The first conductive plugs are contacted by the first level of metal and the second conductive plugs are contacted by the second level of metal. The thickness of the plated conductive material provides a self aligned process for reducing the aspect ratio of the conductive plugs.

REFERENCES:
patent: 6121086 (2000-09-01), Kuroda et al.
patent: 6333222 (2001-12-01), Kitazawa et al.
patent: 6506647 (2003-01-01), Kuroda et al.
patent: 6518130 (2003-02-01), Ohno
patent: 2004/0235259 (2004-11-01), Celii et al.
patent: 2006/0211231 (2006-09-01), Asano et al.

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