Dual-gate metal-oxide-semiconductor device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S140000, C438S286000, C438S335000, C438S454000

Reexamination Certificate

active

07579245

ABSTRACT:
An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A non-uniformly doped channel region of the first conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on the upper surface of the semiconductor layer. A first gate is formed on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region, and at least a second gate formed on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region. The second gate has a length which is substantially greater than a length of the first gate, the first and second gates being electrically isolated from one another.

REFERENCES:
patent: 4288801 (1981-09-01), Ronen
patent: 5252848 (1993-10-01), Adler et al.
patent: 6825531 (2004-11-01), Mallikarjunaswamy
patent: 7126193 (2006-10-01), Baiocchi et al.

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