Memory circuitry with data validation

Details Memory circuitry with data validation Memory circuitry with data validation

2004-10-01

2009-02-03

Chaudry, M. Mujtaba K (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S725000, C714S718000

Reexamination Certificate

active

07487415

ABSTRACT:
Memory circuitry is augmented with data validation circuitry that is closely coupled to the memory circuitry so that data read out of the memory for use in a validation operation does not have to pass through or to general-purpose routing or logic circuitry before it can be used by the data validation circuitry. The data validation circuitry compares the data read from the memory to other signals to determine whether or not there is a match. The data validation circuitry is preferably programmable to select which bits of a word read from the memory will actually be used in the data validation operation.

REFERENCES:
patent: 4855954 (1989-08-01), Turner et al.
patent: 4896296 (1990-01-01), Turner et al.
patent: 7225373 (2007-05-01), Edwards et al.

Affiliated with

Also associated with

Rating

Memory circuitry with data validation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory circuitry with data validation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory circuitry with data validation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4070622