Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-03-27
2009-10-06
Ellis, Kevin (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C714S731000, C714S718000, C714S729000, C713S500000, C327S202000, C327S203000, C327S238000, C327S218000, C327S255000, C327S115000, C327S198000, C375S344000, C375S355000, C326S016000, C365S201000, C324S765010
Reexamination Certificate
active
07600167
ABSTRACT:
A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of the first feedback circuit, based on the logic level of a first clock signal. The second latch has a second feedback circuit and a second selecting circuit which selects an output signal of the first latch and an output signal of the second feedback circuit based on the inverted logic level in case of the first latch. The first feedback circuit has a third selecting circuit which selects one of an output signal of the first latch and a second data input signal based on the logic level of a second clock signal, and outputs a signal selected by the third selecting circuit to the first selecting circuit.
REFERENCES:
patent: 11-174123 (1999-07-01), None
patent: 2003-43114 (2003-02-01), None
patent: 2004-37264 (2004-02-01), None
Ellis Kevin
Merant Guerrier
NEC Corporation
Young & Thompson
LandOfFree
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