Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-11-15
2009-02-17
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07493539
ABSTRACT:
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.
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“Two techniques for minimizing power dissipation in scan circuitsduring test application” by Chakravarty et al. This paper appears in: Test Symposium, 1994., Proceedings of the Third Asian Publication Date: Nov. 15-17, 1994 On pp. 324-329 ISBN: 0-8186-6690-0 INSPEC Accession No. 4868998.
Bassuk Lawrence J.
Brady W. James
Britt Cynthia
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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