Transistors with stressed channels

Details Transistors with stressed channels Transistors with stressed channels

2006-05-22

2009-08-04

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S623000, C257SE29122

Reexamination Certificate

active

07569896

ABSTRACT:
A MOS device having optimized stress in the channel region and a method for forming the same are provided. The MOS device includes a gate over a substrate, a gate spacer on a sidewall of the gate wherein a non-silicide region exists under the gate spacer, a source/drain region comprising a recess in the substrate, and a silicide region on the source/drain region. A step height is formed between a higher portion of the silicide region and a lower portion of the silicide region. The recess is spaced apart from a respective edge of a non-silicide region by a spacing. The step height and the spacing preferably have a ratio of less than or equal to about 3. The width of the non-silicide region and the step height preferably have a ratio of less than or equal to about 3. The MOS device is preferably an NMOS device.

REFERENCES:
patent: 4788160 (1988-11-01), Havemann et al.
patent: 5516711 (1996-05-01), Wang
patent: 5972762 (1999-10-01), Wu
patent: 5998839 (1999-12-01), Cho
patent: 6017801 (2000-01-01), Youn
patent: 6165880 (2000-12-01), Yaung et al.
patent: 6191462 (2001-02-01), Chen-Hua
patent: 6207519 (2001-03-01), Kim et al.
patent: 6329257 (2001-12-01), Luning et al.
patent: 6368926 (2002-04-01), Wu
patent: 6498067 (2002-12-01), Perng et al.
patent: 6642122 (2003-11-01), Yu
patent: 6747373 (2004-06-01), Hu et al.
patent: 6870179 (2005-03-01), Shaheed et al.
patent: 6911376 (2005-06-01), Yoo
patent: 6914309 (2005-07-01), Koga
patent: 7253481 (2007-08-01), Wang et al.
patent: 7361973 (2008-04-01), Chidambarrao et al.
patent: 2002/0048898 (2002-04-01), Li
patent: 2003/0073270 (2003-04-01), Hisada et al.
patent: 2004/0063289 (2004-04-01), Ohta
patent: 2005/0258515 (2005-11-01), Chidambarrao et al.
patent: 2006/0131648 (2006-06-01), Ahn et al.
patent: 2006/0220113 (2006-10-01), Tamura et al.
patent: 2006/0231826 (2006-10-01), Kohyama
Ge, C.-H., et al., “Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering,” IEDM, IEEE, 2003, pp. 73-76.
Thompson, S. E., et al., “A 90-nm Logic Technology Featuring Strained-Silicon,” IEEE Transactions on Electron Devices, vol. 51, No. 11, Nov. 2004, pp. 1790-1797.
Thompson, S., et al., “MOS Scaling: Transistor Challenges for the 21st Century,” Intel Technology Journal Q3'09, pp. 1-19.

Affiliated with

Also associated with

Rating

Transistors with stressed channels does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Transistors with stressed channels, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transistors with stressed channels will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4062496