Method of manufacturing a multiple port memory having a...

Details Method of manufacturing a multiple port memory having a... Method of manufacturing a multiple port memory having a...

2006-01-10

2009-02-03

Menz, Douglas M (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S246000, C257S302000, C257SE21652

Reexamination Certificate

active

07485525

ABSTRACT:
An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors connected together as a unitary source of capacitance. A first access transistor is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.

REFERENCES:
patent: 6015985 (2000-01-01), Ho et al.
patent: 6504204 (2003-01-01), Hsu et al.
patent: 6833305 (2004-12-01), Mandelman et al.
patent: 2001/0023956 (2001-09-01), Collins et al.
patent: 2004/0219747 (2004-11-01), Lin et al.

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