Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-02-20
2008-11-11
Nguyen, Tuan H (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S221000, C438S296000
Reexamination Certificate
active
07449378
ABSTRACT:
The present invention provides a technique for forming a CMOS structure including at least one pFET that has a stressed channel which avoids the problems mentioned in the prior art. Specifically, the present invention provides a method for avoiding formation of deep canyons at the interface between the active area and the trench isolation region, without requiring a trench isolation pulldown, thereby eliminating the problems of silicide to source/drain shorts and contact issues. At the same time, the method of the present invention provides a structure that allows for a facet to form at the spacer edge, retaining the Miller capacitance benefit that such a structure provides. The inventive structure also results in higher uniaxial stress in the MOSFET channel compared to one which allows for a facet to grow at the trench isolation edge.
REFERENCES:
patent: 6828209 (2004-12-01), Maruo
patent: 2004/0113174 (2004-06-01), Chidambarrao et al.
patent: 2005/0156274 (2005-07-01), Yeo et al.
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patent: 2006/0121688 (2006-06-01), Ko et al.
patent: 2006/0202301 (2006-09-01), Ohta et al.
Chidambarrao Dureseti
Greene Brian J.
International Business Machines - Corporation
Nguyen Tuan H
Schnurmann H. Daniel
Scully , Scott, Murphy & Presser, P.C.
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