Shift register, scanning line driving circuit, matrix type...

Details Shift register, scanning line driving circuit, matrix type... Shift register, scanning line driving circuit, matrix type...

2006-08-08

2008-12-09

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C345S098000, C345S099000

Reexamination Certificate

active

07464312

ABSTRACT:
The invention provides a shifter register comprising: a plurality of shift circuit blocks connected in series, each of which includes a predetermined even-number of shift unit circuits; a plurality of clock decision circuit, each of which is provided for each of a plurality of the shift circuit blocks and receives internal condition signals from even-numbered shift unit circuits included in a corresponding shift circuit block and an internal condition signal from the last shift unit circuit included in a preceding shift circuit block, each of the clock decision circuit outputting an operation allowance signal when at least one of the internal condition signals has a first level; and a plurality of clock control circuits, each of which is provided for each of a plurality of the shift circuit blocks and performs a clock signal output operation when the operation allowance signal is supplied from a corresponding clock decision circuit commonly connected to another shift circuit block.

REFERENCES:
patent: 6894674 (2005-05-01), Nakajima et al.
patent: 7245281 (2007-07-01), Sekido et al.
patent: 7248243 (2007-07-01), Murakami et al.
patent: 7284170 (2007-10-01), Whetsel
patent: 11-134893 (1999-05-01), None
patent: 2004-127509 (2004-04-01), None
patent: 2005-134194 (2005-05-01), None

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