High performance MOSFET comprising a stressed gate metal...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Reexamination Certificate

active

07470943

ABSTRACT:
The present invention relates to a semiconductor device that comprises at least one field effect transistor (FET) containing a source region, a drain region, a channel region, a gate dielectric layer, a gate electrode, and one or more gate sidewall spacers. The gate electrode of such an FET contains an intrinsically stressed gate metal silicide layer, which is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating stress in the channel region of the FET. Preferably, the semiconductor device comprises at least one p-channel FET, and more preferably, the p-channel FET has a gate electrode with an intrinsically stressed gate metal silicide layer that is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating compressive stress in the p-channel of the FET.

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patent: 6420766 (2002-07-01), Brown et al.
patent: 6914303 (2005-07-01), Doris et al.
patent: 6977194 (2005-12-01), Belyansky et al.
patent: 2003/0040158 (2003-02-01), Saitoh
patent: 2005/0082616 (2005-04-01), Chen et al.
patent: 2005/0093021 (2005-05-01), Ouyang et al.
patent: 2005/0093059 (2005-05-01), Belyansky et al.

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