Layout structure for ESD protection circuits

Details Layout structure for ESD protection circuits Layout structure for ESD protection circuits

2006-08-29

2008-12-16

Ngo, Ngan (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S361000, C257SE27016

Reexamination Certificate

active

07465994

ABSTRACT:
A layout structure for an ESD protection circuit includes a first MOS device area having a first and second doped regions of the same polarity disposed at two sides of a first conductive gate layer, and a third doped region disposed along the first doped region at one side of the first conductive gate layer. The third doped region has a polarity different from that of the first and second doped regions, such that the third doped region and the second doped region form a diode for enhancing dissipation of ESD current during a negative ESD event.

REFERENCES:
patent: 2006/0097322 (2006-05-01), Kwak et al.
patent: 2006/0157791 (2006-07-01), Lee et al.
patent: 2006/0249792 (2006-11-01), Kim et al.
patent: 2007/0034956 (2007-02-01), Lee et al.
patent: 2007/0181948 (2007-08-01), Liaw et al.
patent: 2007/0241407 (2007-10-01), Kim et al.
patent: 2008/0023767 (2008-01-01), Voldman

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