Memory device and method having data path with multiple...

Details Memory device and method having data path with multiple... Memory device and method having data path with multiple...

2007-12-04

2008-11-25

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189030, C365S189020, C365S189170, C365S189180, C365S189120, C365S220000, C365S221000

Reexamination Certificate

active

07457172

ABSTRACT:
A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

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