Double data rate system

Details Double data rate system Double data rate system

2006-08-30

2008-12-30

Suryawanshi, Suresh K (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S500000, C327S158000

Reexamination Certificate

active

07472304

ABSTRACT:
An extendible timing architecture for an integrated circuit is disclosed. The extendible timing architecture provides metal programmable components for use with different operational clock frequencies. In some embodiments the architecture utilizes master/slave DLLs with a double data rate memory circuit.

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