Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-10-20
2008-08-19
Louis-Jacques, Jacques (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000, C714S702000, C714S718000, C714S720000, C714S728000, C714S733000, C714S734000, C714S738000, C714S742000, C714S743000, C711S100000, C711S200000, C365S201000
Reexamination Certificate
active
07415649
ABSTRACT:
The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-conductor component are able to be tapped and emitted at corresponding outputs of the semi-conductor component test device, whereby the shift register comprises at least one further memory device, from which a further pseudo-random value (VAR) is able to be tapped and whereby a device is provided, with which the further pseudo-random value (VAR) can selectively, if needed, be emitted at at least one corresponding further output of the semi-conductor component test device.
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Infineon - Technologies AG
Louis-Jacques Jacques
Slater & Matsil L.L.P.
Trimmings John P
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