Self-resetting, self-correcting latches

Details Self-resetting, self-correcting latches Self-resetting, self-correcting latches

2005-10-03

2008-08-26

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S797000

Reexamination Certificate

active

07418641

ABSTRACT:
A latch circuit having three latch stages generates a majority output value from the stages, senses when the latch stage outputs are not all equal, and feeds the majority output value back to inputs of the latch stages to reload the latch stages. The latch circuit uses a not-equal gate whose output is an error signal that can be monitored to determine when a single-event upset has occurred. A master stage is controlled by a first multiplexer which receives one system clock signal, while a slave stage is controlled by a second multiplexer which receives another system clock signal, and the latch stage outputs are connected to respective inputs of the not-equal gate, whose output is connected to second inputs of the multiplexers. The latch circuit is part of a latch control system, and reloading of the latch stages takes less than one cycle of the system clock (less than 500 picoseconds).

REFERENCES:
patent: 5307142 (1994-04-01), Corbett et al.
patent: 6028983 (2000-02-01), Jaber
patent: 6127864 (2000-10-01), Mavis et al.
patent: 6504410 (2003-01-01), Waldie et al.
patent: 6504411 (2003-01-01), Cartagena
patent: 6538488 (2003-03-01), Zhang et al.
patent: 6826090 (2004-11-01), Chu et al.

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