Self-synchronizing pseudorandom bit sequence checker

Details Self-synchronizing pseudorandom bit sequence checker Self-synchronizing pseudorandom bit sequence checker

2003-08-28

2008-08-12

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S744000, C714S739000

Reexamination Certificate

active

07412640

ABSTRACT:
Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In an aspect of the invention, a PRBS checking technique includes the following steps/operations. For a given clock cycle, the presence of an error bit in the PRBS generated by the device is detected. The error bit represents a mismatch between the PRBS input to the device and the PRBS output from the device. Then, propagation of the error bit is prohibited for subsequent clock cycles. The prohibition step/operation may serve to avoid multiple errors being counted for a single error occurrence and/or masking errors in the PRBS output by the device.

REFERENCES:
patent: 3648237 (1972-03-01), Frey, Jr. et al.
patent: 3694757 (1972-09-01), Hanna, Jr.
patent: 4139147 (1979-02-01), Franke
patent: 4627057 (1986-12-01), Schmidt et al.
patent: 4639548 (1987-01-01), Oshima et al.
patent: 4771463 (1988-09-01), Beeman
patent: 5163069 (1992-11-01), Hayashi
patent: 5282211 (1994-01-01), Manlick et al.
patent: 5283831 (1994-02-01), Cook et al.
patent: 5321754 (1994-06-01), Fisher et al.
patent: 5334962 (1994-08-01), Higgins et al.
patent: 5390199 (1995-02-01), Ajima et al.
patent: 5392289 (1995-02-01), Varian
patent: 6215876 (2001-04-01), Gilley
patent: 6396889 (2002-05-01), Sunter et al.
patent: 6684350 (2004-01-01), Theodoras et al.
patent: 7168027 (2007-01-01), Lee et al.
patent: 2002/0063553 (2002-05-01), Jungerman
patent: 2002/0065621 (2002-05-01), Jungerman
patent: 2004/0019844 (2004-01-01), Goodnow et al.
patent: 2005/0027922 (2005-02-01), Kim
patent: 2005/0058080 (2005-03-01), Fiddes et al.
patent: 2005/0071399 (2005-03-01), Bonaccio et al.
patent: 1 281 390 (1972-07-01), None
patent: 2003018996 (2003-03-01), None
“Built-in testable error detection and correction” by Katoozi et al. Solid-State Circuits, IEEE Journal of Publication Date: Jan. 1992, vol. 27, Issue: 1 on pp. 59-66 ISSN: 0018-9200 INSPEC Accession No. 4123101.
Oliver Kromat et al., “A 10-Gb/s Silicon Bipolar IC for PRBS Testing,” IEEE Journal of Solid-State Circuits, vol. 33, No. 1, pp. 76-85, Jan. 1998.

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