Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-09-14
2008-10-07
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C382S144000, C430S005000
Reexamination Certificate
active
07434195
ABSTRACT:
A method of generating a mask for use in an imaging process pattern. The method includes the steps of: (a) obtaining a desired target pattern having a plurality of features to be imaged on a substrate; (b) simulating a wafer image utilizing the target pattern and process parameters associated with a defined process; (c) defining at least one feature category; (d) identifying features in the target pattern that correspond to the at least one feature category, and recording an error value for each feature identified as corresponding to the at least one feature category; and (e) generating a statistical summary which indicates the error value for each feature identified as corresponding to the at least one feature category.
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Hsu Duan-Fu Stephen
Hsu Michael
Laidig Thomas
Shi Xuelong
Wampler Kurt E.
ASML Masktools B.V.
Pillsbury Winthrop et al.
Whitmore Stacy A
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