Fully stable clock domain synchronization technique for...

Details Fully stable clock domain synchronization technique for... Fully stable clock domain synchronization technique for...

2004-05-20

2008-05-20

Elamin, A. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C375S368000

Reexamination Certificate

active

07376855

ABSTRACT:
Input/output data transmission between a transmitting integrated circuit and a receiving integrated circuit requires a clock domain synchronizer to synchronize incoming data aligned to a clock signal of the transmitting integrated circuit to a clock signal of the receiving integrated circuit. During a start-up routine, the clock domain synchronizer propagates a pre-determined pattern of data bits through a first circuit path designed to reduce or eliminate metastability. During a normal operations mode, the clock domain synchronizer synchronizes the data signal to the clock signal of the receiving integrated circuit through a second circuit path.

REFERENCES:
patent: 6714612 (2004-03-01), Chaudry
patent: 6928573 (2005-08-01), Wong
patent: 6970049 (2005-11-01), Hipp
patent: 7120216 (2006-10-01), Shirota et al.
patent: 2003/0081713 (2003-05-01), Pontius et al.
patent: 2004/0027166 (2004-02-01), Mangum et al.

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