Semiconductor memory device having self-aligned charge...

Details Semiconductor memory device having self-aligned charge... Semiconductor memory device having self-aligned charge...

2004-12-01

2008-03-18

Landau, Matthew C. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE29309, C257S314000

Reexamination Certificate

active

07345336

ABSTRACT:
A semiconductor memory device having a self-aligned charge trapping layer and a method of manufacturing the same in which a consistent length of an ONO layer is ensured. Here, an insulating stacked structure is self-aligned to a bottom surface of conductive spacers.

REFERENCES:
patent: 5652179 (1997-07-01), Strifler et al.
patent: 6335554 (2002-01-01), Yoshikawa
patent: 6812097 (2004-11-01), Shibata
patent: 7015541 (2006-03-01), Kim et al.
patent: 2003/0032243 (2003-02-01), Ogura et al.
patent: 2003/0134475 (2003-07-01), Hofmann et al.
patent: 15-258128 (2003-09-01), None
patent: 15-258132 (2003-09-01), None
patent: 15-282744 (2003-10-01), None
patent: P2003-0019585 (2003-03-01), None
Li et al. Damascene W/TiN Gate Mosfets with Improved Performance. IEEE Transactions on Electron Devices, vol. 49, No. 11, Nov. 2002.
Lubarsky et al. Quantitative evaluation of local charge trapping in dielectric stacked gate structures using Kelvin probe force microscopy. J. Vac. Sci. Technol. B 20(5), Sep./Oct. 2002.

Affiliated with

Also associated with

Rating

Semiconductor memory device having self-aligned charge... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having self-aligned charge..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having self-aligned charge... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3977659