Method of forming an interconnect structure

Details Method of forming an interconnect structure Method of forming an interconnect structure

2006-06-15

2008-09-23

McDonald, Rodney G (Department: 1795)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S694000, C438S696000, C438S685000, C438S785000, C204S192300

Reexamination Certificate

active

07427568

ABSTRACT:
A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.

REFERENCES:
patent: 4599135 (1986-07-01), Tsunekawa et al.
patent: 4874493 (1989-10-01), Pan
patent: 5089442 (1992-02-01), Olmer
patent: 5108543 (1992-04-01), Suzuki et al.
patent: 5445699 (1995-08-01), Kamikawa et al.
patent: 5614055 (1997-03-01), Fairbairn et al.
patent: 5720821 (1998-02-01), Halpern
patent: 5893758 (1999-04-01), Sandhu et al.
patent: 5983906 (1999-11-01), Zhao et al.
patent: 6030881 (2000-02-01), Papasouliotis et al.
patent: 6077786 (2000-06-01), Chakravarti et al.
patent: 6100200 (2000-08-01), Van Buskirk et al.
patent: 6117781 (2000-09-01), Lukanc et al.
patent: 6136685 (2000-10-01), Narwankar et al.
patent: 6144894 (2000-11-01), Nguyen
patent: 6176983 (2001-01-01), Bothra et al.
patent: 6211040 (2001-04-01), Liu et al.
patent: 2004/0077161 (2004-04-01), Chan et al.
patent: 0591082 (1994-04-01), None
patent: 04-007825 (1992-01-01), None
patent: WO 99/27579 (1999-06-01), None
patent: WO 99/47728 (1999-09-01), None
PCT Search Report, International Patent Application No. PCT/US02/30278, mail date Dec. 19, 2002.
Van Zant, Peter; “Microchip Fabrication 2000”; McGraw-Hill, Fourth Ed. pp. 401-403.
Notification of Second Office Action dated May 9, 2008 for Chinese Patent Application No. 02819959.6 (APPM/4727CHIN).

Affiliated with

Also associated with

Rating

Method of forming an interconnect structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming an interconnect structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming an interconnect structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3977040