Methods of forming semiconductor constructions

Details Methods of forming semiconductor constructions Methods of forming semiconductor constructions

2006-04-25

2008-09-02

Ho, Tu-Tu V (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21655, C257S296000, C257S300000, C257S330000, C257S401000

Reexamination Certificate

active

07419871

ABSTRACT:
The invention includes a method in which a semiconductor substrate is provided to have a memory array region, and a peripheral region outward of the memory array region. Paired transistors are formed within the memory array region, with such paired transistors sharing a source/drain region corresponding to a bitline contact location, and having other source/drain regions corresponding to capacitor contact locations. A peripheral transistor gate is formed over the peripheral region. Electrically insulative material is formed over the peripheral transistor gate, and also over the bitline contact location. The insulative material is patterned to form sidewall spacers along sidewalls of the peripheral transistor gate, and to form a protective block over the bitline contact location. Subsequently, capacitors are formed which extend over the protective block, and which electrically connect with the capacitor contact locations. The invention also includes semiconductor constructions.

REFERENCES:
patent: 2002/0011619 (2002-01-01), Ohkawa
patent: 2006/0270153 (2006-11-01), Lee

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