Monitoring the state vector of a test access port

Details Monitoring the state vector of a test access port Monitoring the state vector of a test access port

2006-01-17

2008-09-23

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S021000, C714S049000, C714S050000, C714S051000, C714S726000, C714S727000, C714S733000, C714S734000, C714S703000, C716S030000, C716S030000

Reexamination Certificate

active

07428674

ABSTRACT:
Monitoring of the state vector of a test access port (TAP) permits isolation of the root cause of improper transitions of the state vector due to various factors, including electrical noise. The test access port includes TCK, TMS, TDI, and TDO. A circuit for monitoring the state vector includes a TAP controller, a storage circuit, and a sampling circuit. The TAP controller updates the state vector for each transition of TCK. The storage circuit stores a value of the state vector responsive to transitions of TCK while a write enable is enabled. To permit generating the write enable without additional pins and without violating a protocol for the test access port, the write enable may be generated in response to a plurality of transitions of TDI of the test access port during an interval in which TMS and TCK of the test access port have no transitions.

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