Static information storage and retrieval – Read/write circuit – Precharge
Patent
1997-01-17
1998-08-11
Kim, Matthew M.
Static information storage and retrieval
Read/write circuit
Precharge
395432, 365233, G11C 1300, G06F 1200
Patent
active
057936889
ABSTRACT:
A multiple latency synchronous dynamic random access memory includes separate two and three latency control circuits driven by an input latch circuit. Commands received at the multiple latency synchronous dynamic random access memory are converted to a separate set of command signals clocked through an input latch circuit by a feedback reset signal, such that commands are pipelined for three latency operation. In response to the command signals, the two latency control circuit produces a set of control signals according to a two latency algorithm. In response to the same command signals, the three latency control circuit independently produces a set of three latency control signals according to a three latency algorithm. In two latency operation, access time for signal development is externally controlled, while in three latency operation access time is internally controlled. In three latency operation, signal development time is determined separately for reads and writes. Also, in three latency operation, data is clocked along a data input path with a write latency. The multiple latency synchronous dynamic random access memory includes a pair of output data paths having different delays, where the data path is selected according to two or three latency operation.
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Kim Matthew M.
Micro)n Technology, Inc.
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