Method of etching dual pre-doped polysilicon gate stacks...

Details Method of etching dual pre-doped polysilicon gate stacks... Method of etching dual pre-doped polysilicon gate stacks...

2003-12-10

2008-03-18

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S584000, C438S714000, C438S689000, C438S738000, C257SE29123, C257SE29126

Reexamination Certificate

active

07344965

ABSTRACT:
A method for making dual pre-doped gate stacks used in semiconductor applications such as complementary metal oxide semiconductor (CMOS) devices and metal oxide semiconductor field effect transistors (MOSFETs) is provided. The method involves providing at least one pre-doped conductive layer, such as poly silicon (poly-Si), on a gate stack and etching by exposing the conductive layer to an etching composition comprising at least one carbon containing gas. The carbon containing gas can be selected from gases having the general formula CxHy, such as, for example, CH4, C2H2, C2H4, and C2H6. The carbon containing gas can further be selected from gases having the general formula CxHyA, wherein A can represent one or more additional substituents selected from O, N, P, S, F, Cl, Br, and I. The processes can result in dual pre-doped gate stacks having essentially vertical sidewalls and further having a width of at least about 3 nm, such as from about 5 nm to about 150 nm.

REFERENCES:
patent: 5242538 (1993-09-01), Hamrah et al.
patent: 5318666 (1994-06-01), Elkind et al.
patent: 5814563 (1998-09-01), Ding et al.
patent: 5876879 (1999-03-01), Kleinhenz et al.
patent: 6162733 (2000-12-01), Obeng
patent: 6849557 (2005-02-01), Ko
patent: 6867450 (2005-03-01), Kito et al.
patent: 6887747 (2005-05-01), Yagishita et al.
patent: 6982223 (2006-01-01), Kim et al.
patent: 2001/0053609 (2001-12-01), Ko
patent: 2004/0038516 (2004-02-01), Kim et al.
patent: 2005/0035409 (2005-02-01), Ko et al.
patent: 2005/0079655 (2005-04-01), Chen et al.
J. Pelletier and M.J. Cooke□□Microwave plasma etching of Si and SiO2 in halogen mixtures: Interpretation of etching mechanisms.□□Jan./Feb. 1989□□Journal of Vacuum Science and Technology B□□American society of Vacuum Society□□□□□□.
O. Joubert, J. Pelletier, C. Fiori and T. A. Nguyen Tan□□Surface mechanisms in O2 and SF6 microwave plasma etching of polymers.□□May 1990□□Journal of Applied Physics□□American institute of Physics.
D. Fuard, O. Joubert, L. Vallier, and M. Bonvalot□□High density plasma etching of low k dielectric polymers in oxygen-based chemistries□□Mar./Apr. 2001□□Journal of Vacuum Science and Technology B□□American Vacuum Society.

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