Method for determining wordline critical dimension in a...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S311000, C257S368000, C257S374000, C257S905000, C257SE21646, C257SE27084, C438S238000, C438S399000

Reexamination Certificate

active

11416551

ABSTRACT:
According to one exemplary embodiment, a method for fabricating a memory array includes forming a number of trenches in a substrate, where the trenches determine a number of wordline regions in the substrate, where each of the wordline regions is situated between two adjacent trenches, and where each of the wordline regions have a wordline region width. The memory array can be a flash memory array. The method further includes forming a number of bitlines in the substrate, where the bitlines are situated perpendicular to the trenches. The method further includes forming a dielectric region in each of the trenches. The method further includes forming a dielectric stack over the bitlines, wordline regions, and trenches. The method further includes forming a number of wordlines, where each wordline is situated over one of the wordline regions. The wordline region width determines an active wordline width of each of the wordlines.

REFERENCES:
patent: 6424001 (2002-07-01), Forbes et al.
patent: 2002/0109173 (2002-08-01), Forbes et al.

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