Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-09-30
2008-09-30
Smith, Matthew S. (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S210000, C438S395000, C257SE27097, C257SE21660
Reexamination Certificate
active
11186810
ABSTRACT:
A gate insulating film is formed on the principal surface of a semiconductor substrate. A silicon film is formed on the gate insulating film. Impurities are doped in the silicon film. In this case, impurities are doped into the silicon film to make a region of the silicon film in the memory cell area have a first impurity concentration and to make a region of the silicon film in the logic circuit area have a second impurity concentration lower than the first impurity concentration. The doped silicon film is patterned. In this case, the silicon film is patterned to leave word lines having the first impurity concentration and serving as gate electrodes in the memory cell area and to leave gate electrodes having the second impurity concentration in the logic circuit area. Source/drain regions of MISFET's are formed in a surface layer of the semiconductor substrate by doping impurities into regions on both sides of each word line in the memory cell area and into regions on both sides of each gate electrode in the logic circuit. The electrical characteristics of the logic circuit area can be improved while the data storage characteristics of memory cells are maintained good.
REFERENCES:
patent: 5194924 (1993-03-01), Komori et al.
patent: 5237187 (1993-08-01), Suwanai et al.
patent: 5444653 (1995-08-01), Nagasawa et al.
patent: 5500387 (1996-03-01), Tung et al.
patent: 5759889 (1998-06-01), Sakao
patent: 5917211 (1999-06-01), Murata et al.
patent: 5953599 (1999-09-01), El-Diwany
patent: 5986309 (1999-11-01), Fujimoto et al.
patent: 5986320 (1999-11-01), Kawano
patent: 6133599 (2000-10-01), Sung et al.
patent: 6144079 (2000-11-01), Shirahata et al.
patent: 6153903 (2000-11-01), Clampitt
patent: 6171942 (2001-01-01), Lee et al.
patent: 6204105 (2001-03-01), Jung
patent: 6492690 (2002-12-01), Ueno et al.
patent: 6815295 (2004-11-01), Ueno et al.
patent: 2007/0126053 (2007-06-01), Lee
patent: 5-226593 (1993-09-01), None
patent: 7-99236 (1995-04-01), None
patent: 7-297393 (1995-11-01), None
patent: 9-181269 (1997-07-01), None
patent: 10-247725 (1998-09-01), None
patent: 10-256511 (1998-09-01), None
Stanley Wolf, Silicon Processing for the VLSI Era, vol. 2: Process Integration, 1990 by Lattice Press, pp. 143-152.
Fujitsu Limited
Maldonado Julio J.
Smith Matthew S.
Westerman, Hattori, Daniels & Adrian , LLP.
LandOfFree
Semiconductor device having both memory and logic circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having both memory and logic circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having both memory and logic circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3929380