Method for designing shallow junction, salicided NMOS transistor

Details Method for designing shallow junction, salicided NMOS transistor Method for designing shallow junction, salicided NMOS transistor

1996-11-25

1998-08-11

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257384, 257382, 257413, 257408, 438236, 438234, 438289, 438649, H01L 2362

Patent

active

057930830

ABSTRACT:
A technique for providing a design window for scaled technologies in which good electrostatic discharge/electrical over stress damage and optimum transistor operation can be achieved without the use of additional masks or design steps. The M, beta, and R.sub.sub parameters of the NMOS transistor 13 and associated parasitic npn transistor 10 are selected to provide the design window.

REFERENCES:
patent: 4442591 (1984-04-01), Haken
patent: 4769686 (1988-09-01), Horiuchi et al.
patent: 5141890 (1992-08-01), Haken
Ting et al., Silicide for Contacts and Interconnects, IEDM, 1984, pp. 110-113.
Leung et al., "Refractory Metal Silicide/N.sup.+ Polysilicon in CMOS/SOS," IEEE .cndot.IEDM Technical Digest, 1980, pp. 827-830.

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