Method of making EEPROM transistor pairs for block alterable...

Details Method of making EEPROM transistor pairs for block alterable... Method of making EEPROM transistor pairs for block alterable...

2008-03-11

2008-03-11

Huynh, Andy (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S201000, C257SE21680, C257SE27103

Reexamination Certificate

active

11126418

ABSTRACT:
A block alterable memory cell has a select control gate extending from a floating gate region to a drain region. The block alterable memory cell comprises a substrate layer that further includes a source implant region, a floating gate transistor region, and a drain implant region. A tunnel oxide layer overlies the substrate layer and is deposited to a thickness of approximately 70 angstroms. A first oxide layer overlies the tunnel oxide layer, with an inter poly layer overlying the first oxide layer, and a second poly layer extending over the floating gate transistor region to an edge of the drain implant region.

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