Method of manufacturing buried bit line flash EEPROM memory cell

Details Method of manufacturing buried bit line flash EEPROM memory cell Method of manufacturing buried bit line flash EEPROM memory cell

1994-11-30

1997-06-03

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438265, 438263, H01L 218247

Patent

active

056354150

ABSTRACT:
A MOSFET device and a method of fabricating an MOSFET device on a lightly doped semiconductor substrate are described. First, form buried bitlines in the substrate. Form conductive, complementary bitline structures formed of doped polycrystalline silicon, the structures having lower surfaces formed on the buried bitlines in electrical contact therewith, and the complementary bitline structures having top surfaces and sidewalls. Form a polysilicon oxide of the doped polycrystalline silicon from the complementary bitline structures over the top surfaces thereof. Oxidize to form tunneling oxide polysilicon oxide sidewall layers adjacent to the complementary bitline structures. Simultaneously, form a tunnel oxide layer over the substrate between the complementary bitline structures. Form floating gates over the tunnel oxide layer and between the sidewall layers. Form an interconductor dielectric layer over the device Finally, form an array of wordlines over the interconductor dielectric layer.

REFERENCES:
patent: 5210046 (1993-05-01), Crotti
patent: 5210047 (1993-05-01), Woo et al.
patent: 5262846 (1993-11-01), Gill et al.
patent: 5279982 (1994-01-01), Crotti
patent: 5381028 (1995-01-01), Iwasa

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