Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-03-25
2008-03-25
Huynh, Andy (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S216000, C438S591000
Reexamination Certificate
active
11478270
ABSTRACT:
A method for forming a metal line in a flash memory device includes sequentially forming a first inter-layer insulation layer, an etch stop layer, a second inter-layer insulation layer, and a hard mask layer over a substrate where a contact plug is formed, etching the hard mask layer to form a hard mask pattern, performing a first etching process on the second inter-layer insulation layer to form a trench exposing a portion of the etch stop layer, performing a second etching process to selectively remove the hard mask pattern and the exposed portion of the etch stop layer, forming a spacer over sidewalls of the trench, and forming a metal line filling the trench to make contact with the contact plug. The hard mask layer and the etch stop layer include substantially the same material. The spacer includes substantially the same material as the first and second inter-layer insulation layers.
REFERENCES:
patent: 6911397 (2005-06-01), Jun et al.
patent: 7183184 (2007-02-01), Doczy et al.
patent: 9-270463 (1997-10-01), None
patent: 2002-0055153 (2002-07-01), None
patent: 10-2004-0102310 (2004-12-01), None
patent: 10-2005-0002024 (2005-01-01), None
Blakely & Sokoloff, Taylor & Zafman
Huynh Andy
Hynix / Semiconductor Inc.
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