Semiconductor memory and method for manufacturing the same

Details Semiconductor memory and method for manufacturing the same Semiconductor memory and method for manufacturing the same

2007-10-09

2007-10-09

Tran, Minh-Loan (Department: 2826)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S259000, C438S262000, C257SE21680

Reexamination Certificate

active

11283984

ABSTRACT:
A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a P type silicon substrate, a control gate CG and a pair of electrically isolated floating gates. Plural projections are formed in the silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate extending in the row direction faces the projection and the floating gate FG1, FG2via an insulation layer. The width W1of the floating gate FG1, FG2in the column direction is larger than the width W2of the control gate CG, so the floating gate FG1, FG2and the control gate CG can be manufactured without the self-align process.

REFERENCES:
patent: 6812518 (2004-11-01), Miida
patent: 6861315 (2005-03-01), Chen et al.
patent: 2004/0169219 (2004-09-01), Miida et al.
patent: 2005/0190605 (2005-09-01), Miida

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