Method and apparatus to deskew data to clock for memory

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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C365S193000, C365S194000

Reexamination Certificate

active

10996936

ABSTRACT:
A description of deskewing data from the clock from a DRAM, such as, but not limited to a DDR3 DRAM is discussed. For example, the differential signals of a strobe and a clock signal are used to create a first and second loops that can be fed back to a memory controller. The two loops are then compared and a delay is added to the strobe until it matches the delay time of the clock.

REFERENCES:
patent: 6646929 (2003-11-01), Moss et al.
patent: 6693436 (2004-02-01), Nelson
patent: 6789209 (2004-09-01), Suzuki et al.
patent: 6795931 (2004-09-01), LaBerge
patent: 6930932 (2005-08-01), Rentschler
patent: 2001/0046163 (2001-11-01), Yanagawa
patent: 2001331365 (2001-11-01), None
patent: 2003173290 (2003-06-01), None
patent: 2004220643 (2004-08-01), None

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