Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-12-11
2007-12-11
Lamarre, Guy (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S724000
Reexamination Certificate
active
10619157
ABSTRACT:
An integrated memory includes command terminals for receiving command signals in a normal operation and in a test operation of the memory, and also a signal terminal for receiving a further signal, which differs from the command signals. Registers store data patterns or data topologies for use in the test operation of the memory. A register decoder circuit serves for the selection of the registers, it being possible for inputs of the register decoder circuit to be connected to the command terminals and to the signal terminal for the purpose of selection of the registers in the test operation. The invention makes it possible, for the test operation, to address an increased number of registers without driving an additional external terminal pin. A method for testing the memory is also provided.
REFERENCES:
patent: 5640509 (1997-06-01), Balmer et al.
patent: 5745403 (1998-04-01), Taylor
patent: 2001/0030888 (2001-10-01), Chang
patent: 2003/0126529 (2003-07-01), Cho
Boldt Sven
Thalmann Erwin
Greenberg Laurence A.
Lamarre Guy
Locher Ralph E.
Radosevich Steven D
Stemer Werner H.
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