Merged MISR and output register without performance impact...

Details Merged MISR and output register without performance impact... Merged MISR and output register without performance impact...

2007-12-04

2007-12-04

Kerveros, James C. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

11056575

ABSTRACT:
The output register of an array and the Multiple Input Signature Register (MISR) logic is implemented with one set of L1/L2master/slave latches and single additional slave latch. This new combined logic uses less critical area on a chip without a performance impact on the array access time or circuit testing.

REFERENCES:
patent: 5553082 (1996-09-01), Connor et al.
patent: 6421794 (2002-07-01), Chen et al.
patent: 2005/0222816 (2005-10-01), Cheng et al.
patent: 2006/0101316 (2006-05-01), Wang et al.

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