Test mask structure

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

Reexamination Certificate

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Details

C257SE21036, C430S030000

Reexamination Certificate

active

10732370

ABSTRACT:
Disclosed is a test mask structure. The test mask structure of the present invention comprises at least an array pattern region, in a certain proportion to the final product, having a first pattern density according to the certain proportion; and at least one test mask pattern region having a second pattern density. In the test mask structure of the present invention, the required pattern density is obtained by adjusting the area of the array pattern region and the area of the test mask pattern region according to the first pattern density and the second pattern density.

REFERENCES:
patent: 6279147 (2001-08-01), Buynoski et al.
patent: 6335560 (2002-01-01), Takeuchi
patent: 6737205 (2004-05-01), Maltabes et al.
patent: 2001/0003054 (2001-06-01), Sumitani
patent: 2003/0229880 (2003-12-01), White et al.
patent: 01186617 (1989-07-01), None
patent: 01251631 (1989-10-01), None
patent: 09311432 (1997-12-01), None
patent: 2001044285 (2001-02-01), None
patent: 2003007678 (2003-01-01), None
patent: WO 01/20646 (2001-03-01), None

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